Field effect transistor with a buried and confined metal plate to control short channel effects

ABSTRACT

A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region of the FET includes a buried and confined metal plate for controlling short channel effects without significantly increasing junction capacitance.

TECHNICAL FIELD

The present invention generally relates to the design of field effecttransistors (FETs) using silicon-on-insulator (SOI) technology and, moreparticularly, to an SOI FET with a structure for controlling shortchannel effects.

BACKGROUND OF THE INVENTION

Conventional or bulk semiconductor devices are formed in semiconductivematerial by implanting a well of either P-type or N-type conductivitysilicon in a silicon substrate wafer of the opposite conductivity. Gatesand source/drain diffusions are then manufactured using commonly knownprocesses. These form devices known as metal-oxide-semiconductor (MOS)field effect transistors (FETs). When a given chip uses both P-type andN-type, it is known as a complimentary metal oxide semiconductor (CMOS).Each of these transistors must be electrically isolated from the othersin order to avoid shorting the circuits. A relatively large amount ofsurface area is needed for the electrical isolation of the varioustransistors. This is undesirable for the current industry goals for sizereduction. Additionally, junction capacitance between the source/drainand the bulk substrate increase power consumption, require higherthreshold voltages, and slows the speed at which a device using suchtransistors can operate (e.g. degrades frequency response). Theseproblems result in difficulties in reducing the size, power consumption,and voltage of CMOS technology devices.

In order to deal with the junction capacitance problem and improvefrequency response, silicon on insulator technology (SOI) has beengaining popularity. A SOI wafer is formed from a bulk silicon wafer byusing conventional oxygen implantation techniques or wafer bondingtechniques to create an insulating buried oxide layer at a predetermineddepth below the surface. Between the buried oxide layer and the surfaceof the SOI wafer is a silicon device layer in which SOI field effecttransistors (FETs) and other SOI structures may be fabricated.

Referring to FIG. 1, a partially depleted SOI FET 10 is shown. The FET10 is fabricated on an SOI wafer 12 which includes a bulk substrate 14,an insulating buried oxide layer 16, and the device layer 18. The FET 10is fabricated within the device layer 18 and includes a source region 20and a drain region 22 each of a first conductivity silicon and a channelregion 24, of the opposite conductivity silicon, positioned between thesource region 20 and the drain region 22. A gate 26 is positioned abovethe channel region 24 and is separated from the channel region 24 by aninsulating gate oxide film 28. In operation, when a charge above athreshold voltage is applied to the gate 25, current flows from a sourceextension region 20′ to a drain extension region 22′ through a narrowdepletion region 24′ just beneath the gate oxide 28.

It is desirable to reduce the size of the FET 10 such that a greaterquantity of such FETs may be fabricated within a particular size wafer.A problem associated with reducing the size of SOI FET structures is areduction in the length of the depletion region 24′ (distance betweenthe source extension 20′ and the drain extension 22′) degrades FETperformance because of a phenomenon known as the short channel effect.When the length of the depletion region 24′ is on the order of 0.2 μm,the potential of both the source region 20 and the drain region 22 willcause depletion within the depletion region 24 independent of thepotential of the gate 26. The depletion regions formed by potential ofthe source region 20 and the drain region 22 may extend entirely throughthe depletion region 24′ permitting current to flow even though thepotential of the gate 26 is below threshold potential in a phenomenonreferred to as punch-through. Additionally, impact ionization within thechannel region 24 caused by the floating body effect further degradesshort channel performance of the FET 10.

It has been found that short channel behavior is governed by the ratioof the depletion region 24 thickness (depth below the gate oxide 28) toits length. As such, decreasing the thickness of the gate oxide region28 enables use of a thinner depletion region 24 for improving shortchannel performance. However, tunneling leakage is a problem with thingate oxide regions 28, particularly when the channel region 24 is P-conductivity silicon.

The thickness of the depletion region 24, can also be decreased byincreasing the doping concentration of the channel region 24. It hasbeen found that the thickness of the depletion region is inverselyproportional to the square root of the channel doping concentration.However, increased doping concentrations tend to increase junctioncapacitance which degrades the FET's frequency response.

Accordingly, there is a strong need in the art for a semiconductor fieldeffect transistor structure which can be scaled to sub-micron dimensionwithout significant performance degradation due to short channel effector increased junction capacitance.

SUMMARY OF THE INVENTION

A first aspect of the present invention is to provide asilicon-on-insulator (SOI) field effect transistor (FET) on an SOI waferwhich includes a silicon device layer separated from a bulk siliconlayer by an insulating layer of silicon dioxide. The SOI FET comprises achannel region of a first conductivity type semiconductor formed in thesilicon device layer. A source region and a drain region, both of asecond conductivity type semiconductor, are formed in the silicon devicelayer on opposing sides of the channel region. A buried and confinedmetal plate region is positioned within the central portion of thecentral channel region. The buried and confined metal plate regionextends between the source region and the drain region and is separatedfrom a top surface of the central channel region leaving a depletionregion there between and is separated from a bottom surface of thechannel region. A gate is positioned above the central channel region,separated from the top surface of the central channel region by a gateoxide layer, for controlling depletion within the depletion region.

The source region and the drain region may include a source extensionregion and drain extension region respectively. Both extension regionsextending into the central channel region adjacent to the top surface ofthe central channel region. The buried and confined metal plate regionextends between the source extension region and the drain extensionregion at a depth that corresponds to the depth of the source extensionregion and drain extension region (e.g. junction depth). Morespecifically, the plate region has a top surface and a bottom surface(defined by a cut-off concentration) both of which are substantiallyparallel with the top surface of the central channel region, and thebottom surface of the plate region is positioned at a depthcorresponding to the junction depth.

In the exemplary embodiment a thickness of the plate region, between thetop surface of the plate region and the bottom surface of the plateregion, is between 50 and 150 angstroms, or more specifically, between80 and 120 angstroms in thickness.

A second aspect of the present invention is to provide a method offabricating an SOI FET. The method comprises: a) forming a body regionwithin a device layer of a silicon on insulator wafer; b) forming a gateover a central channel region of the body region; c) forming a sourceregion and a drain region on opposing sides of the central channelregion; and d) forming a heavily doped buried and confined metal plateregion within the central channel region and extending between thesource region and the drain region.

The step of forming the body region may include forming an insulatingtrench about a periphery of the body region to isolate the body fromother portions of the silicon device layer.

The step of forming the source region and the drain region may include:i) lightly doping the source region and the drain region with aconductivity enhancing impurity utilizing the gate over the centralchannel region as a mask of the central channel region; ii) formingspacers on the sides of the gate; and iii) doping the source region andthe drain region utilizing the gate and the spacers as a mask of thecentral channel region. More specifically, the step of lightly dopingthe source region and the drain region may be performed with an implantenergy which provides for the impurity atoms to implant into the sourceregion and drain region within a source extension region and a drainextension region both adjacent to the surface of the wafer and having ajunction thickness less than a thickness of the device layer. Moreover,the step doping the source region and the drain region may be performedwith an implant energy which provides for the impurity atoms to implantthe entire thickness of the source region and drain region.

The step of forming the heavily doped buried and confined plate regionmay include utilizing an implant energy which concentrates the impurityatoms at a depth below the surface of the wafer which corresponds to thejunction depth of the source extension region and the drain extensionregion. The thickness of the concentration region of the impurity atomsmay be between 50 and 150 angstroms in thickness, and, morespecifically, may be between 50 and 150 angstroms in thickness.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional FET fabricated usingSOI technology;

FIG. 2 is a cross-sectional view of an SOI FET in accordance with oneembodiment of the present invention;

FIG. 3a is a cross section diagram showing a step in the fabrication ofthe SOI FET in accordance with this invention;

FIG. 3b is a cross section diagram showing a step in the fabrication ofthe SOI FET in accordance with this invention;

FIG. 3c is a cross section diagram showing a step in the fabrication ofthe SOI FET in accordance with this invention;

FIG. 3d is a cross section diagram showing a step in the fabrication ofthe SOI FET n accordance with this invention;

FIG. 3e is a cross section diagram showing a step in the fabrication ofthe SOI FET in accordance with this invention;

FIG. 3f is a cross section diagram showing a step in the fabrication ofthe SOI FET in accordance with this invention; and

FIG. 4 is a flow chart showing exemplary processing steps in thefabrication of the SOI FET in accordance with this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention will now be described in detail with reference tothe drawings. Referring to FIG. 2, a partially depleted silicon oninsulator (SOI) FET 30 is shown in accordance with this invention.

FET 30 includes a lightly doped P-conductivity body region 50 separatingan N-conductivity source region 32 and an N-conductivity drain region34. The source region 32 and the drain region 34 extend from the surfaceof the wafer 52 to a buried oxide layer 44. The profile of both thesource region 32 and the drain region 34 is such that a thin sourceextension region 32′ and a thin drain extension region 34′ extend intothe body region 50 just beneath the surface 52. The portion of the bodyregion 50 which is between the source extension region 32′ and the drainextension 34′ is a depletion region 36. Above the depletion region 36 isan insulating gate oxide layer 28 and an N+silicon gate 40.

Within the body region 50 positioned just below the depletion region 36and at the same depth as each of the source extension region 32′ and thedrain extension region 34′ is a buried and confined metal plate region42. The metal plate region 42 extends between the bottom of the sourceextension region 32′ and the bottom of the drain extension region 34′.The metal plate region 42 has a thickness on the order of 100 Angstromsand is heavily P- doped (e.g. doping concentration on the order of1×10¹⁹ atoms per cm³.

It should be appreciated that a charge on either (or both) of the sourceregion 32 and the drain region 34 may cause depletion along the sourcejunction and drain junction respectively. The metal plate region 42,with the high doping concentration, prevents such depletion fromextending entirely across the depletion region 36 thereby limiting shortchannel effect. More specifically, the metal plate region 42 can supporta higher depletion charge per unit of cubic volume so that the totalvolume of the depletion region caused by the source region 32 and thedrain region 34 is minimized. Because the metal plate region 42 is verythin, the junction between the high doping concentration plate region 42and each of the source region 32 and the drain region 34 is very small.As such, junction capacitance is not significantly increased as it wouldbe if the entire body region were heavily doped.

Referring to the flowchart of FIG. 4 in conjunction with the crosssectional diagrams of FIG. 3a-FIG. 3f, exemplary processing steps forfabricating FET 30 are shown. Step 70 represents fabricating an SOIwafer 58 with the insulating buried oxide layer 44 separating thesilicon device layer 46 from the base substrate 48 as shown in FIG. 3a.Common methods for fabricating an SOI wafer include a separation byimplantation of oxygen (SIMOX) process in which oxygen is implanted intoa bulk wafer at the desired depth and a wafer bonding process in whichtwo wafers are bonded together with the oxide layer sandwiched therebetween and one of the two wafers is then polished (or cut using aSmartCut® process) to the desired device layer thickness.

Step 72 represents isolating the FET 30 from other structures which maybe fabricated in the silicon device layer 46. Isolation is accomplishedby etching an insulating trench 54 into the silicon device layer 46about the periphery of FET 30 and filling the insulating trench 54 withan insulating compound as shown in FIG. 3b. More specifically, etchingthe insulating trench 54 may be accomplished by forming a siliconnitride mask over the surface of the SOI wafer 58 to define and exposethe area corresponding to the insulating trench 54. A layer of siliconnitride is then formed by depositing a layer of silicon nitride on thetop surface of the SOI wafer and patterning and etching the siliconnitride using conventional photolithography techniques to form a siliconnitride mask over FET 30. Once masked, an anisotropic etch with aetching compound such as hydrogen bromide (Hbr) is preferably used toetch the insulating trench 54 in the region.

After etching the insulating trench 54, the silicon nitride mask can beremoved using a wet chemical mechanical polish and the insulating trenchfilled with an insulating compound such as silicon dioxide. Conventionalfilling techniques may include filling the trench 54 with a compoundsuch as SiH4 or TEOS and performing a thermal oxidization to oxidizesuch compound to form silicon dioxide. Other back filling techniquesknown to those skilled in the art may also be used.

Step 74 represents forming a polysilicon gate 40 over the central regionof the FET 30 as is shown in FIG. 3c. More specifically, a conventionalthermal oxidization process is used to grow a gate oxide layer 28(comprising silicon dioxide), on the surface of the wafer 58. A layer ofpolysilicon is deposited on the surface of the gate oxide layer 28 usinglow pressure chemical vapor deposition (LPCVD) as is known by thoseskilled in the art. Conventional photolithography techniques are thenused to pattern and mask the polysilicon gate 40 and anisotropic etchingtechniques are used to remove un-masked polysilicon thereby forming thepolysilicon gate 40.

Step 76 represents lightly doped drain (LDD) implant of the sourceregion 32 and the drain region 34 with a conductivity enhancing impurityof the same conductivity as the source region 32 and drain region 34(e.g. opposite conductivity as the channel region 50) to form the sourceextension 32′ and the drain extension 34′ as is shown in FIG. 3d. Morespecifically step 76 represents implanting an n-conductivity impuritysuch as phosphorus or arsenic with a dosage of about 1×10¹⁴ to 1×10¹⁶atoms/cm² and a energy of about 500 eV to 10 KeV.

Step 78 represents forming insulating spacers 56 along the sides of thepolysilicon gate 40. Spacers 56 may be formed by depositing a layer ofsilicon nitride or silicon dioxide approximately 300 to 1000 angstromsin thickness over the entire surface of the waver 30 and subsequentlyanisotropically etching the deposited layer to expose the top surface ofthe polysilicon gate 40 and the top surface of each of the source region32 and the drain region 34 while leaving spacers 56.

After formation of the spacers 56, step 79 represents implanting thesource region 32 and the drain region 34 with an n-conductivity impuritysuch as phosphorus or arsenic. The polysilicon gate 40 functions todefine and mask the central channel region 50 of the FET 30 duringimplant of the source region 32 and drain region 34.

Step 80 represents formation of the buried and confined metal plate 42.More specifically, formation of the buried and confined metal plate 42includes a pre amorphize step with a heavy species such as Ge or Sifollowed by an implant step with a species such as BF2/Boron or Indiumat a dosage of 1×10¹² to 1×10¹⁴ atoms per cm³ within the metal plateregion 42. Step 81 represents activation with a solid phase epitaxyprocess.

The FET structure in accordance with this invention provides forreducing short channel effects without significantly increasing junctioncapacitance thereby permitting fabrication of FETs which are smaller andhave a better frequency response. Although the invention has been shownand described with respect to certain preferred embodiments, it isobvious that equivalents and modifications will occur to others skilledin the art upon the reading and understanding of the specification. Thepresent invention includes all such equivalents and modifications, andis limited only by the scope of the following claims.

What is claimed is:
 1. A silicon-on-insulator field effect transistor comprising: a) a channel region of a first conductivity type semiconductor formed in a silicon layer over an insulator layer; b) a source region and a drain region both of a second conductivity type semiconductor formed in the silicon layer on opposing sides of the channel region, i) the source region including a source extension region extending into the channel region adjacent to a top surface of the channel region and having a depth below the top surface that is less than a thickness of the silicon layer; ii) the drain region including a drain extension region extending into the channel region adjacent to the top surface of the channel region and having a depth below the top surface that is less than a thickness of the silicon layer; c) a plate region within a central portion of the channel region extending between the source extension and the drain extension, separated from both the top surface of the channel region and the bottom surface of the channel region, and extending between the source region and the drain region wherein the plate region includes a top surface and a bottom surface both of which are substantially parallel with the top surface of the central channel region and the bottom surface of the plate region is positioned at a depth corresponding to the depth of the source extension region and the drain extension region; and d) a gate positioned above the channel region, separated from the top surface of the channel region by a gate oxide layer, and controlling depletion within a portion of the central channel region between the plate region and the top surface of the central channel region.
 2. The silicon-on-insulator field effect transistor of claim 1, wherein a thickness of the plate region between the top surface of the plate region and the bottom surface of the plate region is between 50 and 150 angstroms in thickness.
 3. The silicon-on-insulator field effect transistor of claim 2, wherein a thickness of the plate region between the top surface of the plate region and the bottom surface of the plate region is between 80 and 120 angstroms in thickness.
 4. A semiconductor device including a plurality of field effect transistors formed on a semiconductor substrate, the device comprising: a) an insulating oxide layer positioned within the semiconductor substrate and separating a device layer portion of the semiconductor substrate form a bulk portion of the semiconductor substrate; b) an insulating trench pattern positioned within the device layer and isolating each of the plurality of field effect transistors and each of the plurality of field effect transistors comprises: i) a channel region of a first conductivity type semiconductor formed in a silicon layer over an insulator layer; ii) a source region and a drain region both of a second conductivity type semiconductor formed in the silicon layer on opposing sides of the channel region; the source region including a source extension region extending into the channel region adjacent to a top surface of the channel region and having a depth below the top surface that is less than a thickness of the silicon layer; the drain region including a drain extension region extending into the channel region adjacent to the top surface of the channel region and having a depth below the top surface that is less than a thickness of the silicon layer; iv) a plate region extending between the source extension and the drain extension within a central portion of the channel region, separated from both a top surface of the channel region and a bottom surface of the channel region, and extending between the source region and the drain region; wherein the plate region includes a top surface and a bottom surface both of which are substantially parallel with the top surface of the central channel region and the bottom surface of the plate region is positioned at a depth corresponding to the depth of the source extension region and the drain extension region; and v) a gate positioned above the channel region, separated from the top surface of the channel region by a gate oxide layer, and controlling depletion within a portion of the channel region between the plate region and the top surface of the channel region.
 5. The semiconductor device of claim 4, wherein a thickness of the plate region between the top surface of the plate region and the bottom surface of the plate region is between 50 and 150 angstroms in thickness.
 6. The semiconductor device of claim 5, wherein a thickness of the plate region between the top surface of the plate region and the bottom surface of the plate region is between 80 and 120 angstroms in thickness. 